FPGA Computer with Custom Assembler, SSE1 Instructions

Tyler McGrew and myself designed and implemented a basic computer architecture on an FPGA (Altera DE2) using the Verilog language for synthesis. It had a reduced instruction set (RISC), and was eventually extended to supporting SSE1 instructions. One of my tasks was to implement the assembler to processes our invented assembly language into actual register-based machine code, which could then be programmed onto the FPGA's ROM section. 
Here's the assembler on GitHUB.